Sun 25 Feb 2018 10:30 - 12:00 at Pacific 2 - Productive parallel programming on FPGA with high-level synthesis Session 2
As the scale of high performance computing systems increases, so does their power consumption, making energy efficiency an increasingly important consideration in their design. While GPUs and custom processors have improved this situation significantly, FPGAs promise another major step in energy efficiency, representing a middle ground between fixed hardware architectures and custom built ASICs. Programming FPGAs has traditionally been done in hardware description languages, requiring extensive hardware knowledge and significant engineering effort. This tutorial shows how high-level synthesis (HLS) can be harnessed to efficiently exploit spatial parallelism on FPGAs, while preserving programmer productivity. Attendees will learn how to target available FPGA resources with high-level C++ constructs, and control and guide the mapping from imperative code to hardware, enabling them to develop massively parallel designs by identifying and implementing patterns suitable for spatial parallelism. We will establish the central concepts of HLS necessary to achieve an efficient hardware implementation, then show how performance modeling and more advanced programming techniques can be used to optimize it further. By enabling the design of efficient FPGA implementations in a high level language, our tutorial seeks to bridge the gap between software and hardware development, allowing programmers from a larger set of backgrounds to begin tapping into the potential of FPGAs.
Sun 25 Feb
|08:30 - 10:00|
|10:30 - 12:00|